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2.
Pin Configurations and Pinouts
Pin
Name
Function
32-lead PLCC
Top view
32-lead PDIP
Top view
V PP
A 0 - A 18
Peak to Peak Voltage
Address Inputs
V PP
A 16
1
2
32
31
V CC
A 18
O 0 - O 7
GND
CE
OE
V CC
Outputs
Ground
Chip Enable
Output Enable
Device Power Supply
A 7
A 6
A 5
A 4
A 3
A 2
A 1
A 0
O 0
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
A 14
A 13
A 8
A 9
A 11
OE
A 1 0
CE
O 7
A 15
A 12
A 7
A 6
A 5
A 4
A 3
A 2
A 1
3
4
5
6
7
8
9
10
11
30
29
28
27
26
25
24
23
22
A 17
A 14
A 13
A 8
A 9
A 11
OE
A 1 0
CE
3.
Switching Considerations
A 0
O 0
O 1
O 2
GND
12
13
14
15
16
21
20
19
18
17
O 7
O 6
O 5
O 4
O 3
Switching between active and standby conditions via the Chip Enable (CE) pin may produce transient voltage
excursions. Unless accommodated by the system design, these transients may exceed datasheet limits, resulting in
device nonconformance. At a minimum, a 0.1 μ F, high-frequency, low inherent inductance, ceramic capacitor should be
utilized for each device. This capacitor should be connected between the V CC and ground terminals of the device — as
close to the device as possible. Additionally, to stabilize the supply voltage level on printed circuit boards with large
EPROM arrays, a 4.7 μ F bulk electrolytic capacitor should be utilized, again connected between the V CC and ground
terminals. This capacitor should be positioned as close as possible to the point where the power supply is connected to
the array.
4.
Block Diagram
V CC
GND
V PP
Data Outputs
O 0 – O 7
OE
CE
A 0 – A 18
Address
Inputs
OE, CE, and
Program Logic
Y Decoder
X Decoder
Output
Buffers
Y-Gating
Cell Matrix
Identification
Atmel AT27C040 [DATASHEET]
0189J–EPROM–10/2012
2
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